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Description: 实现FPGA对Cypress公司的68013A款的USB芯片应用于SLAVEFIFO的读操作，使用verilog语言编写，Q2开发环境。-FPGA to realize the company s 68013A paragraph Cypress USB chip used SLAVEFIFO read operation, using verilog language, Q2 development environment.
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Size: 403456 |
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Description: 采用MATLAB实现定点的FFT运算，但是仿真硬件结构的IP核调用以及误差产生模式，用于仿真FPGA实现FFT运算的效果和误差来源。-FPGA to realize the company s 68013A paragraph Cypress USB chip used SLAVEFIFO read operation, the fixed-point implementation using MATLAB FFT operation, but the hardware structure of the IP core simulation calls and error generation model for simulating the effects of FPGA implementation and FFT computation sources of error.
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Size: 2048 |
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Description: 与Cpress CY8013所对应的 FPGA端的开发
使用NIOSII NIOSII 连续往USB FIFO 端点里灌数据 上位机不断的接收
陪和我的上位程序可以达到30Mbyte/s 需要上位机程序的去搜索TestUSBSpeedMFCNovember -upload-And Cpress CY8013 corresponding end FPGA development using NIOSII NIOSII continuous irrigation to USB FIFO endpoint data in the host computer receives constantly accompany and my host program can reach 30Mbyte/s PC program needs to search TestUSBSpeedMFCNovember-upload
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Size: 25570304 |
Author: kn |
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Description: 关于USB开发的verilog开发程序，非常的全面，学习FPGA开发时用得着。-About USB development verilog development process, very comprehensive, learning FPGA development time worthwhile.
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Size: 94208 |
Author: 李阳 |
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Description: 基于verilog语言的，FPGA程序实现电脑与FPGA串口的数字传输，硬件设备为EP1C3T100C8，usb转RS232芯片为FT232BM，-Based verilog language, FPGA program FPGA serial digital transmission of computer and hardware devices to EP1C3T100C8, usb to RS232 chip FT232BM,
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Size: 598016 |
Author: FT_Young |
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Description: DLP Discovery 4100
数字微镜(DMD)空间光开关光调制器开发系统
1.全面兼容德州仪器TI DLP D4100 开发系统. 能够支持1920X1080 DMD(DMD微镜为10.6微米,本征分辨率为1920X1080)
数字微镜(DMD)空间光开关光调制器开发系统
2. 1024 X 768 的DMD(4:3)有两种微镜结构，一种是13.68 微米，
对角线长度为0.7 英寸；另一种是10.8 微米的，对角线长度为0.55
英寸；我们系统都能支持所有主流分辨率DMD
3. 支持USB2.0 高速度传输图片和控制信号
4. 开放式控制软件基于Windows XP 全速度USB驱动,在Visual
Basic 下编制,开发式接口, 易于高精度光学科研实验
5. 提供丰富的Windows XP 的USB 控制程序和API 开发系统
6. 支持XGA, 1080p 和1920x1200 分辨率单个微镜精确控制
7. 开放式FPGA 架构, 提供示例FPGA 的二次开发选择和客户
定制功能
8. 高速二进和任意灰度制图片显示 输入输出系统触发,支持通
用客户顶GPIO 口设置.
9. 我们能为客户提供全程独特定做和设计服务.
应用:
结构光投影,激光全息,无掩模光刻,高光谱成像,激光光束校形,
3D 测量和3D 打印机技术, 光谱分析.
Jefferson_zhao@163.com-DLP DMD Discovery 4100
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Size: 6450176 |
Author: wucow |
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Description: 用于FPGA和USB通信芯片之间的高速并行数据通信，包括FPGA程序代码和USB固件程序，-For high-speed parallel data communication between FPGA and USB communications chips, including FPGA and USB firmware code,
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Size: 1625088 |
Author: 庄晓奇 |
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Description: usb fpga 1 2 source code forusb ı p core
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Size: 6303744 |
Author: tuna |
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Description: 用于开发上位机的fpga的USB内置固件驱动-usb firmware driver
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Size: 102400 |
Author: 小苏打 |
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Description: USB 1.1 FS only design has been implemented and tested on lattice FPGA. Setup is done for USB 2.0 High speed (480Mbps)mode
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Size: 5007360 |
Author: HANUMAN |
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Description: Wishbone规范具有如下特点:简单、紧凑，需要很少的逻辑门 完整的普通数据据传输总线协议，包括单个读写、快传输、读一修改一写周期、事件周期 数据总线宽度可以是8-64位 支持大端(big-endian)和小端(litle-endian)，接口自动完成两者之间的转换。支持存储器映射、FIFO存储器、交叉互联 握手协议，允许速率控制 可以达到每个时钟周期进行一次数据传输 支持普通周期结束、重试结束、错误结束等总线周期形式 支持用户自定义的标志:采用MASTER/SLAVE体系结构 支持多点进程(Multi-MASTER):仲裁算法用于定义 支持各种各样的IP核互联，包括USB、双向总线、复用器互联等 同步逻辑设计 非常简单的时序标准 与硬件实现技术无关(FPGA, ASIC等) 与设计工具无关。
相对于其他的IP核接口规范来说，Wishbone接口规范具有简单、开放、高效、利于实现等特点而且完全免费，并没有专利保护。基于上述优点，因此采用Wishbone总线进行接口设计。本文对Wishbone总线接口的设计参考了OpenCore上的有关设计。-
Wishbone specification has the following characteristics : a simple , compact, and requires very little logic gates complete common data bus data transfer protocols, including single reader , fast transmission, read-modify- write cycle, the event cycle data bus width can be 8-64 bit support big-endian (big-endian) and the small end (litle-endian), the interface automatically convert between the two. Support memory mapping , FIFO memory , cross interconnection handshake protocol that allows rate control every clock cycle to achieve a data transfer support normal cycle ends , retry the end , wrong end of the bus cycle and other forms support for user-defined flags : The MASTER/SLAVE architecture supports multi- process (Multi-MASTER): arbitration algorithm is used to define support a variety of IP cores interconnected , including USB, bi-directional bus , multiplexer interconnection , etc. synchronous logic design very simple timing standards technology-indepe
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Size: 12288 |
Author: 程浩武 |
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Description: 本程序功能是在FPGA上nios处理器的usb接口程序。-The program features in the FPGA on the Nios processor usb interface program.
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Size: 4096 |
Author: ymarki |
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Description: 用VHDl语言实现USB与FPGA接口模块代码-VHDl language with USB and FPGA Interface Module code
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Size: 1024 |
Author: Diego |
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Description: 本源码通过USB接口芯片实现了FPGA与计算机的通信，具有完整的工程文件以及源码，经验证成功地实现了该芯片的功能。-The source through the USB interface chip FPGA communication with the computer, with a complete project file and source code, proven successful realization of the chip.
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Size: 1642496 |
Author: zhu yue |
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Description: 基于FPGA的软核设计可以实现串口通信和usb通信的双向传输，以及可以在软核基础上实现无线以太等其他通信-FPGA-based soft-core design can be achieved usb communication serial communication and two-way transmission, and can be implemented in other communications such as wireless Ethernet based on soft-core
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Size: 19982336 |
Author: 王琦 |
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Description: 这是我自己做的项目，CY7C68013与FPGA中的USB程序，希望站长能通过-This is my own project, CY7C68013 USB and FPGA program in the hope that through the station
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Size: 161792 |
Author: lfj |
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Description: 一个上位机和FPGA通信的程序，usb芯片 是FFT2232-A PC and FPGA communication procedures, usb chip is FFT2232
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Size: 10643456 |
Author: 王太兴 |
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Description: 数字微镜DMD空间光调制器控制平台G4100可以实现如下功能：1、兼容德州仪器TI D4100 开发系统。能够支持1920 X 1080分辨率DMD (DMD微镜为10.6微米,本征分辨率为1920X1080)；同时还能支持1024 X 768分辨率的DMD（有两种微镜结构，一种是13.68 微米，对角线长度为0.7 英寸；另一种是10.8 微米的，对角线长度为0.55 英寸）；
2、支持USB2.0 高速传输图片和控制信号，具有内同步和外同步功能，同步脉冲电平标准为CMOS 3.3V；
3、开放式控制软件基于Windows XP 全速度USB驱动，程序在VS2010下编写，开放式接口, 有利于二次开发；
4、提供丰富的Windows XP 的USB控制程序和API开发系统；
5、支持XGA，1080p 和1920 x 1200 分辨率单个微镜精确控制；
6、开放式FPGA 架构，提供示例FPGA 的二次开发选择和客户定制功能；
7、高速二进制和任意灰度图片显示；
8、对比度：超过2000：1；
9、波段：350nm--2700nm 可见光；
10、微镜二进制翻转频率：播放帧频可设置，目前可做到5K；
11、微镜任意时间锁定。
-DMD digital micromirror spatial light modulator control platform G4100 can achieve the following functions: 1, compatible with Texas Instruments TI D4100 development system. Can support 1920 X 1080 resolution DMD (DMD micromirror 10.6 microns, the intrinsic resolution of 1920X1080) while also supporting a resolution of 1024 X 768 DMD (micromirror structure, there are two, one is 13.68 microns, for diagonal length of 0.7 inches Another is 10.8 microns, the diagonal length of 0.55 inches) 2, support USB2.0 high speed transmission of images and control signals with the synchronization and external synchronization, sync pulse level standards as CMOS 3.3V 3, open Windows XP-based control software full speed USB drive, programming in VS2010, open interfaces, help secondary development 4, provides a wealth of Windows XP' s USB control program and API development system 5, supports XGA, 1080p and 1920 x 1200 resolution single micromirror precise control 6, open FPGA architecture, pr
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Size: 630784 |
Author: 刘明 |
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Description: 基于NIOS II的USB驱动设计，在FPGA平台上加入NIOS处理器以及需要的ip构成嵌入式系统实现USB数据传输-NIOS II design is based on the USB drive, and the need to join NIOS processor on an FPGA platform ip constitute embedded systems USB Data Transfer
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Size: 3072 |
Author: ddiao |
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Description: 16通道逻辑分析仪，100M，FPGA代码，包括FIFO，dram，usb等-16 channel logic analyzer, 100 m, the FPGA code, including FIFO, DRAM, usb, etc
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Size: 13312 |
Author: 钢灵海川 |
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